Synchronous sequential systems rely on globally synchronized clocks. A delay-locked loop (DLL) is one type of circuit capable of generating these clocks. DLLs have proven advantageous because of their ability to achieve low clock skew distributions. They are also suitable for use in high-speed circuits that require clock signals with programmable duty cycles and delay.
In spite of their advantages, many DLL circuits demonstrate an unsatisfactory level of stability control. For example, in these circuits tail current used to control the delay cells is maintained at a constant value. As a result, frequency variations translate into proportional changes in the DLL output amplitude. This situation, shown in FIG. 1, has proven to be undesirable for many high-speed applications.